The VHDL/Verilog Graphical IDE (VGI) fundamentally changes the way you create and maintain the most complex HDL designs.
Switch from dozens of HDL files with thousands of lines each, to the same way one plans and designs a Hardware IP block: visually as individual interconnected blocks, each with a differentiated function, the way the brain sees designs.
Breakthrough separation of functionality from timing.
While new engineers need reading long source code files to understand an IP before trying to improve it, VGI allows seeing the design, drawing the improvement of the IP, surgically, while guaranteeing timing relationships between all old/new signals are automatically maintained.
The VGI IDE allows creating the same complex designs with markedly less man-months of time, while being significantly more maintainable and understandable.
